With increasingly high complexity and increasingly small size of integrated circuit design, an isolation technology plays an increasingly important role in integrated circuit manufacturing. The isolation technology in the CMOS (Complementary Metal Oxide Semiconductor) process mainly includes dielectric material isolation, reverse PN junction isolation and the like, wherein the dielectric material isolation has an outstanding performance in eliminating parasitic transistors, reducing the working capacitance, inhibiting the latch-up effect of MOS (Metal Oxide Semiconductor) transistors and the like. In preparation processes of 3-0.35 μm, a local oxidation of silicon (LOCOS) process is widely used, but this preparation process has the following defects: (1) field silicon dioxide invades an active region due to a bird's beak structure; (2) the narrow width effect of an active device is caused by redistribution of field oxygen implantation in a high-temperature process; (3) the field silicon dioxide becomes thin in a narrow isolated region; and (4) an uneven surface shape is produced. These defects are particularly outstanding in preparation process nodes of 0.18 μm and less, so that the LOCOS preparation process is no longer appropriate. With the development of devices from deep submicron to nanometer, a shallow trench isolation (STI) technology has substituted the LOCOS technology and becomes a mainstream isolation technology. Compared with the LOCOS technology, the STI technology has the advantages of complete evenness and good latch-up resistance, and completely has no bird's beak; and the STI technology may avoid the high temperature process, reduce the junction spacing and the junction capacitance, ensure the region of the active region and improve the integration level.
With reduction of the area of the active region of a device, the influence of the STI stress on the performance of the device would not be neglected, so that the performance of the device is strongly related to the area of the active region of the device and the position of the device in the active region; and the STI stress not only affects the threshold voltage of the device, but also affects the carrier mobility of the device. An existing commercial MOSFET (Metal Oxide Semiconductor Field Effect Transistor) standard model BSIM4 is molded on the STI stress effect, and mainly involves the influence of the stress on the threshold voltage and the mobility. According to researches, the temperature has a great influence on the STI stress effect, the low temperature would strengthen the STI stress and then increase the influence on the performance of the device, and this is not sufficiently considered in the standard model BSIM4, so that extracted model parameters are not accurate enough.